1. Field of the Invention
The present invention relates generally to phase locked loops, and in particular, to a stabilization technique for phase-locked frequency synthesizers.
2. Description of the Related Art
(Note: This application references a number of different publications as indicated throughout the specification by reference numbers enclosed in brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References.” Each of these publications is incorporated by reference herein.)
Phase-locked loops (PLLs) typically suffer from a trade-off between the settling time and the ripple on the control voltage, limiting the performance that can be achieved in terms of channel switching speed and output sideband magnitude in radio frequency (RF) synthesizers.
Accordingly, what is needed in the art is a loop stabilization technique that yields a small ripple while achieving fast settling. The present invention satisfies this need.